A central processing unit (CPU) within a computer system typically accesses one or more memory arrays when executing programmed instructions of a CPU process. In some prior art arrangements, base and offset operand addition is used to address content within caches as well as data or instructions within other CPU memory units or memory arrays. In one particular arrangement, a 64-bit base operand and a 64-bit offset operand for a given programmed instruction are summed or added together to arrive at an effective address used to access a memory array. Such CPU arrangements can take at least two cycles to access the memory array, a first cycle to add the base and offset operands and a second cycle to access the memory array based on the results of the addition.
To decrease memory access latency, content from a main memory unit can be stored in smaller-sized caches that are indexed by summing portions of the base and offset operands called index bits. A decode of the sum of the index bits points to a particular wordline or row of memory array cells that is “turned on” to access the content of the cell. This is referred to as a memory array access. The addition of the smaller operands as well as the use of the smaller-sized memory arrays results in more efficient memory access.
Further optimizations have been made by using speculative access methods, whereby multiple speculative accesses to a memory array are made without knowing a least significant bit (LSB) carry-in to the sum of the index bits. Once the LSB is known, content from one of the speculative accesses is selected. Thus, a shortcoming of speculative access methods, as compared to methods that take longer but require only a single memory access to obtain the memory content, is the additional dynamic power consumption used to turn on multiple wordlines.
The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like reference numbers indicate similar elements. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present disclosure.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Also, the functions included in the flow diagrams do not imply a required order of performing the functionality contained therein.